1. Field of the Invention
The present invention relates to a semiconductor memory device that has a function for testing a defective cell in memory cells constituting a DRAM (Dynamic Random Access Memory).
Priority is claimed on Japanese Patent Application No. 2007-056376, filed Mar. 6, 2007, the content of which is incorporated herein by reference.
2. Description of Related Art
In recent years, in response to the advancement in the capacity of servers and personal computers, a reduction in the chip size is required in order to achieve a reduction in manufacturing cost and in the size of devices.
Accordingly, in order to meet the above customer requirement, there have been ongoing developments in micro fabrication for chip size reduction, and for improving performance such as processing speed performance.
However, while micro fabrication processes and processing speeds are improving, an increase in defects in memory cells is of concern, and in order to improve the efficiency of a test for detecting defective memory cells, there has been proposed a semiconductor memory device that has a memory cell testing circuit (for example, Patent Document 1).
FIG. 4 shows a configuration example of a sense amplifier and memory cells in a conventional semiconductor memory device. As an example, this circuit diagram of the conventional example shows a semiconductor memory device comprising a sub word driver 210 or a sub word driver 211 provided on each of both sides of a sense amplifier 240, and memory cells connected thereto. The sub word driver 210 corresponds to a memory array 250, and the sub word driver 211 corresponds to a memory array 251. In this circuit diagram of FIG. 4, a sub word line WL1 selected for example by the sub word driver 210 reads a memory cell A, and the data is outputted to a data line DT and amplified in the sense amplifier 240.
Moreover, one of the factors of the above defects in memory cells is that the capacitance value of a capacitance plate (capacitor) Cs of the memory cell is small.
However, in a selection test being currently performed, a memory cell having a capacitor with a lower capacitance value compared to that of a standard range (that is, a defective cell) is likely to pass the test with a high possibility.
In order to detect a defect of a small capacitance value of a capacitor, currently a non standard accelerated test is performed to make a capacitance plate with a low capacitance value defective.
[Patent Document 1] Japanese Unexamined Patent Application, First Publication No. 2004-103119
However, as can be seen from the waveform diagram of the conventional word line and data lines shown in FIG. 5, there is a problem in that in a current memory cell structure, even for a memory cell formed with a capacitance value Cs that is smaller compared to that of the design standard range as with the defective cell A which is the detection target of the present invention, if the memory cell has a certain level of capacitance value, the sense amplifier amplifies a minute voltage difference between data lines, and thereby the memory cell passes the selection test and it is not detected as a defective cell.
Furthermore, in a memory cell having a sufficient retention time in a refreshing cycle (having a potential performance of tREF), there is a shortcoming in that it is more difficult to detect a defect.
Therefore, in the conventional technique, as mentioned above, acceleration of the internal power supply voltage, and the tREF value are set much longer than those in the product standard, creating a situation where an unreasonable design needs to be made, and there is also a problem of an overkill in acceleration tests. The possibility of fabricating defective cells will also increase with the future growth in the capacity of memory devices.